Data Patterns hiring Freshers For Engineer Trainee – HDD (FPGA Design) with BE(ECE/EEE) – 2019/2019 batch Passout in Chennai.
|Job Role||Engineer Trainee – HDD (FPGA Design)|
|Salary||Best In Industry|
- Should have good knowledge in basics of Analog & Digital Electronics
- Should have expertise in VHDL/Verilog
- Should have expertise in Xilinx/Altera FPGAs
- Should have expertise in using Xilinx Vivado and Altera Quartus
- Should be capable of implementing complex FPGA designs individually
- Should have expertise in High Speed Serial Interfaces, PCIe, DDR3, Gigabit Ethernet, Signal Processing Algorithms.
- Expertise in using Verification tools
- Expertise in using MATLAB (Optional)
- Expertise with Debugging tools like Chipscope and Signal Tap analyzer.